Optical Interconnects: Photonic Communication for AI Clusters

Electrical interconnects based on copper transmission lines encounter severe physical limitations as data rates increase and cluster sizes expand toward exascale performance levels. The resistance of copper conductors rises significantly at high frequencies due to the skin effect, which confines current flow to a thin outer layer of the conductor, thereby increasing effective resistance and signal attenuation. Dielectric losses within the insulating materials surrounding the conductors further degrade signal integrity, introducing inter-symbol interference that necessitates complex digital signal processing to recover transmitted data accurately. These physical constraints force electrical links to consume increasing amounts of power per bit of transmitted data to maintain signal quality over distance, creating a power wall where the energy required for communication exceeds the energy budget available for computation. As artificial intelligence workloads demand higher bandwidth between processing nodes, the density of electrical traces becomes a limiting factor because crosstalk between adjacent lines restricts the number of high-speed lanes that can be routed through a given space. Optical interconnects address these core bandwidth, latency, and power constraints by utilizing light to transmit data through optical fibers or waveguides, which exhibit significantly lower loss and higher bandwidth-distance products compared to electrical cables.

Silicon photonics enables the fabrication of optical components directly on semiconductor chips using standard complementary metal-oxide-semiconductor manufacturing infrastructure, allowing for the mass production of photonic integrated circuits alongside electronic logic. This technology uses the high refractive index contrast between silicon and silicon dioxide to confine light within sub-micron scale waveguides, facilitating the routing of optical signals across a chip with minimal bending loss. The compatibility with existing CMOS foundries allows designers to integrate photonic devices such as modulators, detectors, and wavelength multiplexers onto the same die or within the same package as application-specific integrated circuits and graphics processing units. This setup reduces the cost and complexity of photonic systems by avoiding the need for discrete optical components assembled manually. Silicon waveguides provide a strong platform for passive routing elements that direct light signals between different functional blocks on the chip with high precision and low propagation loss. The ability to manufacture these devices at wafer scale using established semiconductor processes ensures that optical interconnects can scale economically to meet the volume demands of large-scale AI clusters.

The core function of a photonic interconnect involves converting electrical signals from compute units into modulated optical carriers, transmitting these signals via waveguides or fibers, and detecting them at the destination to reconvert them back into electrical signals. Signal encoding relies on manipulating properties of laser light such as intensity, phase, or polarization to represent digital data; common formats include pulse-amplitude modulation such as PAM4 for shorter reach links and coherent modulation for longer distances requiring high spectral efficiency. Modulators alter the phase or amplitude of the light passing through them by changing the refractive index of the silicon waveguide through mechanisms like the plasma dispersion effect, where injecting or depleting charge carriers changes the optical properties of the material. Mach-Zehnder modulators split light into two arms and apply a phase shift to one arm before recombining them, converting phase modulation into amplitude modulation through interference. Ring resonator modulators offer a smaller footprint by connecting at specific wavelengths and shifting the resonance frequency through carrier injection, thereby modulating the intensity of light passing through the ring when tuned on or off resonance. On-chip lasers remain a significant technical challenge because silicon is an indirect bandgap material, making it highly inefficient at emitting light compared to direct bandgap semiconductors like indium phosphide.

Most current systems use external laser sources coupled into silicon photonic circuits via edge couplers or grating couplers, which introduce coupling losses and add complexity to the packaging process. Connecting with efficient light sources directly onto silicon substrates requires heterogeneous setup techniques where III-V materials are bonded onto the silicon wafer and processed to form laser cavities. These external laser sources often reside in separate modules or shelves within the rack, delivering light to the compute nodes through optical fibers, a configuration that helps manage thermal dissipation by isolating the heat-generating lasers from the sensitive compute ASICs. Photonic integrated circuits integrate these modulators, multiplexers, detectors, and passive routing elements onto a single die to create a complete optical transceiver subsystem that fits within the footprint of a standard chip package. Wavelength Division Multiplexing increases fiber capacity by transmitting multiple data channels simultaneously over a single waveguide using different wavelengths of light, effectively multiplying the bandwidth of a single optical fiber by the number of channels employed. Arrayed waveguide gratings or echelle gratings serve as multiplexers and demultiplexers to combine and separate these different wavelengths at the transmitter and receiver ends of the link.

This technique allows terabit-per-second aggregate links to be achievable through the dense setup of photonic transceivers without requiring a proportional increase in the number of physical fibers. Dense WDM systems utilize narrow channel spacing to maximize the number of channels within the low-loss transmission windows of optical fibers. Co-packaged optics places these optical engines adjacent to or within the same package as ASICs or GPUs to minimize electrical trace length and reduce the input-output power consumed by driving signals across long electrical channels. Optical switching fabrics route data via light paths through the network without converting signals to the electrical domain at every intermediate node, reducing latency and energy per bit compared to traditional electronic packet switching. These fabrics utilize optical cross-connects that can establish and reconfigure physical light paths between endpoints under the control of a software-defined network management plane. By maintaining the data in the optical domain throughout the switch fabric, the system eliminates the power overhead and latency associated with optical-to-electrical and electrical-to-optical conversions at each hop.

This approach is particularly beneficial for large-scale AI clusters where traffic patterns involve large, sustained flows of data between specific nodes during training operations. Optical interconnects operate as point-to-point links or switched topologies, with control planes managing wavelength allocation and path setup to ensure efficient utilization of the optical bandwidth. Key components within a photonic communication system include the laser source, modulator, waveguide, multiplexer or demultiplexer, photodetector, driver electronics, and transimpedance amplifier circuits. The driver electronics amplify the electrical signals from the compute unit to levels sufficient to drive the modulator, while the transimpedance amplifier converts the small current generated by the photodetector back into a usable voltage signal for the receiver circuitry. System-level connection requires careful co-design of electrical serializer/deserializer circuits, photonic layers, packaging materials, and thermal management solutions to ensure signal integrity across the entire link. Optical input/output must support standardized protocols such as Ethernet, Compute Express Link, and Universal Chiplet Interconnect Express to interface seamlessly with existing compute and memory hierarchies used in AI accelerators.

The power budget for an optical link includes laser wall-plug efficiency, insertion loss across components such as waveguides and couplers, receiver sensitivity, and digital signal processing overhead for equalization and error correction. Insertion loss is the reduction in optical power between the input and output of a component or link, serving as a critical parameter for link budget planning to ensure sufficient signal reaches the detector with an adequate signal-to-noise ratio. Silicon photonics involves the fabrication of optical devices using silicon-on-insulator wafers and standard semiconductor processes such as lithography, etching, and deposition. Photonic wire bonding provides a method to connect separate photonic chips or fibers with micron-scale precision using direct-write lithography, creating flexible optical connections between different dies within a package. Early research in the 2000s demonstrated proof-of-concept silicon photonic modulators and detectors that showed the feasibility of working with optical functionality on silicon chips. The period from 2010 to 2015 saw the rise of pluggable optical transceivers such as quad small form-factor pluggable modules, which became the standard for data center networking, providing a convenient interface for replacing optical components.

The years from 2018 to 2020 marked an industry shift toward co-packaged optics, driven by hyperscalers facing input/output power walls and the formation of consortiums like the Consortium for On-Board Optics and the Optical Internetworking Forum to define standards for working with optics closer to the switch ASIC. During this time, it became clear that pluggable modules would not scale efficiently to the bandwidth densities required for next-generation AI clusters due to the power and distance limitations of electrical connections between the module and the chip. Commercial deployments of co-packaged optics in AI accelerators began appearing between

Coupling losses between fibers and chips limited manufacturing yield because sub-micron alignment accuracy was required to efficiently couple light from a fiber mode into a silicon waveguide mode. Economic hurdles included high upfront non-recurring engineering costs for custom photonic integrated circuit designs and labor-intensive packaging and testing processes that differed significantly from standard semiconductor assembly. Flexibility issues arose as fiber count and connector density became limiting factors in large-scale systems, while optical switching added complexity in control logic and fault tolerance mechanisms required to maintain network reliability. Material limitations involved reliance on indium phosphide for lasers and germanium for detectors, introducing supply chain risks and compatibility challenges with standard silicon fabrication fabs that typically do not process these materials. Electrical serializer/deserializer scaling pursued through pulse-amplitude modulation schemes and advanced equalization techniques hit a power-per-bit wall beyond speeds of 112 gigabits per second per lane, making further increases in electrical bandwidth prohibitively expensive in terms of energy consumption. Pluggable optics faced limitations for AI clusters due to high power consumption per module, large form factor occupying space on server faceplates, and limited bandwidth density relative to co-packaged alternatives.

Free-space optical interconnects were considered for board-to-board links but abandoned due to alignment sensitivity and environmental reliability issues such as dust accumulation interfering with the optical path. Polymer waveguides were explored for low-cost optical routing on circuit boards but lacked thermal stability and connection compatibility with high-density silicon photonics. AI model training demands exponentially growing inter-node communication for collective operations such as all-reduce during distributed training across thousands of GPUs. Electrical input/output consumes a significant portion of total system power in large clusters, making optical alternatives economically imperative to reduce operational expenditures and improve performance per watt. Hyperscalers and chipmakers face diminishing returns from Moore’s Law scaling regarding transistor performance, shifting focus toward system-level innovation via optics to extract more performance from existing process nodes. Societal need exists for faster, more efficient AI infrastructure to support real-time inference applications, scientific simulation tasks, and edge deployment scenarios where latency and power efficiency are critical constraints.

NVIDIA’s current AI platforms utilize high-speed pluggable optics for system-scale networking while relying on proprietary copper-based links for internal GPU-to-GPU communication within a single server or chassis. Intel’s Gaudi3 accelerators utilize high-bandwidth optical interconnects for scale-out networking to connect multiple accelerator cards across different servers. Ayar Labs develops TeraPHY chiplets for prototype systems, targeting high bandwidth density via multi-wavelength wavelength division multiplexing integrated directly into a chiplet format compatible with standard packaging processes. Meta and Google test optical switching in data center fabrics to reduce hop count and improve bisection bandwidth by creating adaptive optical paths between top-of-rack switches. Dominant architectures involve co-packaged optics with external laser shelves and discrete photonic integrated circuits, using mature silicon photonics foundries to manufacture the optical components. Appearing technologies include fully integrated on-chip lasers using bonded III-V materials and optical circuit switching for agile topology reconfiguration without traffic disruption.

Alternative approaches include board-level optical backplanes using embedded waveguides in the circuit board substrate, though limited by manufacturing complexity and signal loss compared to fiber-based solutions. Silicon wafers and silicon-on-insulator substrates are widely available from semiconductor suppliers, while indium phosphide and germanium wafers represent specialty materials with concentrated suppliers leading to potential supply chain fragility. Fiber alignment and packaging equipment markets are dominated by specialized vendors providing high-precision active alignment machines capable of sub-micron placement accuracy. Testing and characterization require specialized photonic automated test equipment, creating a hindrance in high-volume production because traditional electronic test handlers cannot measure optical parameters such as insertion loss or wavelength drift. Intel pursues vertical connection across silicon photonics, advanced packaging, and AI chips with a strong intellectual property portfolio in co-packaged optics and wavelength division multiplexing technologies. NVIDIA focuses on system-level adoption of optical interconnects in AI platforms and partnerships with optical engine suppliers to integrate external solutions into their systems.

AMD invests in optical input/output technologies for future MI series accelerators and collaborates with research consortia to develop open standards for chiplet-based optical communication. Cisco and Juniper develop optical switching fabrics for AI networking and integrate photonics into router architectures to reduce power consumption in core network switches. Academic labs and industry consortia develop heterogeneous connection techniques and novel laser setup methods to improve performance and reduce costs. Software stacks must adapt to optical topology constraints, requiring photonic-aware implementations for routing algorithms and congestion control protocols that account for the properties of optical links such as asymmetry or switching latency. Thermal management systems require redesign to handle localized heating from laser sources and high-density photonic integrated circuits, which generate heat in concentrated areas, unlike distributed electronic logic. Standards bodies define electrical-optical co-packaging interfaces, power delivery models, and mechanical form factors to ensure interoperability between components from different vendors.

Data center cabling infrastructure shifts from copper twinax cables to single-mode fiber with tighter bend radius specifications and cleaner handling requirements due to the sensitivity of optical connections to contamination and macro-bending loss. The decline in demand for high-speed electrical serializer/deserializer intellectual property and pluggable transceiver markets drives shifts in business models among component suppliers. New business models include photonic chiplet foundries offering manufacturing services for fabless designers, optical interconnect-as-a-service offerings, and specialized packaging houses focusing exclusively on photonic assembly. Job displacement occurs in traditional connector and cable manufacturing sectors, while growth happens in photonic design automation, test engineering roles, and packaging technology development. Traditional key performance indicators such as gigabits per second per millimeter of interconnect width and picojoules per bit are becoming insufficient for evaluating system performance in the context of advanced AI clusters where total system throughput and energy efficiency matter more than individual link metrics. New metrics are needed, including optical power budget margin to account for aging effects, wavelength utilization efficiency within a band, and thermal drift tolerance indicating stability under varying load conditions.

System-level benchmarks must include end-to-end latency under optical switching configurations, not just link-layer throughput measurements that ignore switching overhead. Reliability metrics must account for aging of laser sources and photodetectors under continuous operation at high temperatures and high optical power densities. Monolithic setup of III-V lasers on silicon via direct bonding or epitaxial growth is a critical research goal that would enable true single-chip optical transceivers without external components. Optical memory interfaces such as photonic DRAM controllers could reduce data movement constraints between processors and memory by providing high-bandwidth, low-latency access to memory banks located off-package. Reconfigurable wavelength-selective switches will enable active bandwidth allocation across AI workloads by dynamically assigning wavelengths to specific communication flows based on real-time demand. Quantum dot lasers offer potential for improved temperature stability and lower threshold currents in future systems compared to traditional quantum well lasers.

Convergence with 2.5D and 3D chiplet packaging will position photonic input/output as a universal interconnect layer across compute, memory, and storage chiplets connected via a silicon interposer or organic substrate. Connection with neuromorphic computing will utilize optical synapses and photonic spiking neurons for ultra-low-latency inference tasks that mimic biological neural networks using light instead of electricity for spike transmission. Synergy with cryogenic computing will rely on low-loss optical links for connecting room-temperature control electronics to superconducting processors operating at millikelvin temperatures where electrical wiring introduces excessive heat load. Key limits exist where diffraction restricts the minimum cross-section of a waveguide, constraining the density of optical channels on a chip, and nonlinear effects occur at high optical power densities causing signal distortion. Workarounds include mode-division multiplexing utilizing different spatial modes within a single waveguide, hollow-core fibers reducing nonlinear interactions, and plasmonic waveguides confining light below the diffraction limit, though these approaches face significant loss and fabrication challenges. Thermal crosstalk between densely packed optical channels requires active cooling solutions or wavelength stabilization loops using thermal tuners to maintain channel alignment as temperature gradients shift the refractive index of the silicon.

Optical interconnects serve as necessary enablers for next-generation AI systems constrained by the physical laws governing electrical conduction. Success hinges on co-optimization across device physics, package design, system architecture, and software layers to fully apply the advantages of photonics. The transition will be gradual, with hybrid electrical-optical systems dominating the adoption phase as optical technologies replace specific constraints in the hierarchy, such as rack-to-rack links, before moving to chip-to-chip communication. Superintelligence systems will require zettaflop-scale compute capabilities with near-instantaneous communication across millions of processing elements distributed across a facility. Optical interconnects will provide the only viable path to sustain bandwidth growth while controlling power and latency at that scale because electrical interconnects cannot support the required bandwidth density over meter-scale distances without excessive power dissipation. Photonic networks will enable novel architectures, such as optically switched memory pools and distributed training with zero-copy data sharing, where data remains in the optical domain while being accessed by multiple compute nodes.

Superintelligence will apply optical interconnects not just for data transfer but as computational substrates, using interference patterns and nonlinear optics for analog or hybrid computing tasks that perform matrix multiplication or convolution operations passively through light propagation. Wavelength-encoded information could support high-dimensional state representation within neural networks, aligning with theoretical models of efficient intelligence that rely on vector symbolic architectures or holographic representations. The physical substrate of communication will become inseparable from the architecture of thought in such systems as the distinction between memory, processing, and communication blurs into a continuous photonic fabric.